Data processor

ABSTRACT

A data processing apparatus constituting a low-cost audio/video data transmission and reception system is disclosed. A reception buffer monitoring circuit  21  monitors the size of receiver data being accumulated in a reception buffer  6 . When the size of accumulated data is found to become higher than a high threshold, the circuit  21  causes a reception clock generation circuit  8  to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit  8 , an audio/video decoder  7  decodes the audio/video data coming from the reception buffer  6 . This invention applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.

TECHNICAL FIELD

[0001] The present invention relates to a data processing apparatus and,more particularly, to a data processing apparatus which is simplystructured to process data.

BACKGROUND ART

[0002]FIG. 1 shows an overall configuration of a conventionalaudio/video data transmission and reception system. On the transmittingside, transmitter audio/video data to be sent out are input to anaudio/video encoder 1. In turn, the audio/video encoder 1 compresses theinput transmitter audio/video data illustratively in MPEG format basedon a clock frequency generated by a transmission clock generationcircuit 2 such as a crystal oscillator. The compressed data areaccumulated in a transmission buffer 3 to absorb clock frequencydifferences. Every time a transmission device 4 sends data to areception device 5, the transmission buffer 3 replenishes thetransmission device 4 with more data. Before transmission, thetransmission device 4 subjects the transmitter data to such processes ascode conversion and modulation.

[0003] On the receiving side, the reception device 5 receives thetransmitter data from the transmission device 4 and restores theoriginal data by subjecting the received data to such processes asdemodulation and decoding. The restored data are accumulated in areception buffer 6. It is assumed that the data transfer rate betweenthe transmission device 4 and the reception device 5 is sufficientlyhigher than the transfer rate of the audio/video data. From thereception buffer 6, the data are forwarded to an audio/video decoder 7in properly timed relation with processing of the latter. Theaudio/video decoder 7 decodes (i.e., decompresses) the data inaccordance with a clock frequency generated by a reception clockgeneration circuit 8.

[0004] With the system in FIG. 1, it is difficult to keep thetransmission clock frequency input to the audio/video encoder 1 exactlythe same as the reception clock frequency entered into the audio/videodecoder 7 because of variations in component parameters incurred duringmanufacturing. The resulting difference in processing speeds causes dataoverflows and underflows in the reception buffer 6, as will be discussedlater with reference to FIGS. 2A through 2F and 3A through 3F. Thefluctuating flow of data causes the audio/video decoder 7 to developirregularities in reproducing the video or audio data.

[0005]FIGS. 2A through 2F illustrate how a data overflow occurs. Anaudio/video encoder synchronizing clock (FIG. 2A) is generatedinternally by the audio/video encoder 1 in keeping with the transmissionclock generated by the transmission clock generation circuit 2. Insynchronism with leading edges of the clock, encoded audio/video data Dn(FIG. 2B) of a fixed length each are accumulated in the transmissionbuffer 3 (of a two-packet size).

[0006] Transmitter data Dn are received by the reception device 5following a predetermined transmission delay (FIG. 2C) and areaccumulated in the reception buffer 6 (FIG. 2D). Receiver data Dn areforwarded from the reception buffer 6 to the audio/video decoder 7 (FIG.7F) whereby the data are decoded and output as receiver audio/videodata.

[0007] An audio/video decoder synchronizing clock (FIG. 2E) is generatedinternally by the audio/video decoder 7 in accordance with the receptionclock generated by the reception clock generation circuit 8. The datainput in synchronism with each leading edge of the clock are decoded bythe audio/video decoder 7. In this example, the audio/video decodersynchronizing clock (FIG. 2E) is lower in frequency than the audio/videoencoder synchronizing clock (FIG. 2A), so that a data overflow takesplace when receiver data Dn+5 are placed into the reception buffer 6.

[0008]FIGS. 3A through 3F depict how a data underflow occurs.Audio/video data are processed in the same manner as with the case inFIGS. 2A through 2F. In this example, the audio/video decodersynchronizing clock (FIG. 3E) is higher in frequency than theaudio/video encoder synchronizing clock (FIG. 3A), so that the receptionbuffer 6 is vacated before the reception of subsequent receiver dataDn+3 (FIG. 3D). With the reception buffer 6 incapable of transferringdata to the audio/video decoder 7 at a leading edge of the audio/videodecoder synchronizing clock (FIG. 3F), a data underflow takes place.

DISCLOSURE OF INVENTION

[0009] The present invention has been made in view of the abovecircumstances and provides a data processing apparatus that constitutesa simply structured, low-cost system capable of preventing dataoverflows and underflows.

[0010] In carrying out the invention and according to a first aspectthereof, there is provided a data processing apparatus including: areceiving element for receiving data; a storing element for storing datareceived by the receiving element; a processing element for processingthe data received by the receiving element; a clock generating elementfor generating a clock for use by the processing element processing thedata received by the receiving element; and a controlling element forcontrolling a frequency of the clock generated by the clock generatingelement in accordance with a size of data stored by the storing element.

[0011] In one preferred structure according to the first aspect of theinvention, the processing element may decode the data received by thereceiving element.

[0012] In another preferred structure according to the first aspect ofthe invention, if the size of data is higher than a first referencevalue, then the controlling element may raise the clock frequency; andif the size of data is lower than a second reference value, then thecontrolling element may lower the clock frequency.

[0013] In a further preferred structure according to the first aspect ofthe invention, the data processing apparatus may further include aseparating element for separating the data received by the receivingelement into a first data item and a second data item; wherein thestoring element may include: a first storing element for storing thefirst data item; and a second storing element for storing the seconddata item; and wherein the processing element may include: a firstprocessing element for processing the first data item; and a secondprocessing element for processing the second data item.

[0014] In an even further preferred structure according to the firstaspect of the invention, if there occurs a difference in totalprocessing time between a transmission block and a reception blockhandling the first data item and the second data item, and if Buf1 isassumed to denote a data size processible by the first processingelement and Bfu2 to represent an average value of the first referencevalue and the second reference value, then the controlling element maycause a center value of a controllable range of data sizes accommodatedby the first storing element to correspond to a sum of Buf1 and Buf2.

[0015] In a still further preferred structure according to the firstaspect of the invention, the first data item and the second data itemmay be made up of an audio data item and a video data item respectively.

[0016] According to a second aspect of the invention, there is provideda data processing method including the steps of: receiving data; storingdata received in the receiving step; processing the data received in thereceiving step; generating a clock for use in the processing stepprocessing the data received in the receiving step; and controlling afrequency of the clock generated in the clock generating step inaccordance with a size of data stored in the storing step.

[0017] According to a third aspect of the invention, there is provided arecording medium which stores a program readable by a computer, theprogram including the steps of: receiving data; storing data received inthe receiving step; processing the data received in the receiving step;generating a clock for use in the processing step processing the datareceived in the receiving step; and controlling a frequency of the clockgenerated in the clock generating step in accordance with a size of datastored in the storing step.

[0018] The data processing apparatus of this invention is characterizedin that the clock frequency is controlled in accordance with the size ofthe data being held in the apparatus.

BRIEF DESCRIPTION OF DRAWINGS

[0019]FIG. 1 is a block diagram showing a typical configuration of aconventional audio/video data transmission and reception system;

[0020]FIGS. 2A through 2F are explanatory views depicting how a dataoverflow occurs in the system of FIG. 1;

[0021]FIGS. 3A through 3F are explanatory views illustrating how a dataunderflow takes place in the system of FIG. 1;

[0022]FIG. 4 is a block diagram indicating a typical configuration of anaudio/video data transmission and reception system embodying theinvention;

[0023]FIG. 5 is a flowchart of steps performed by the system of FIG. 4;

[0024]FIG. 6 is an explanatory view sketching frequencies of a receptionclock generated by a reception clock generation circuit included in FIG.4;

[0025]FIG. 7 is an explanatory view graphically showing sizes of dataaccumulated in a reception buffer included in FIG. 4;

[0026]FIG. 8 is a block diagram depicting a typical configuration ofanother audio/video data transmission and reception system embodying theinvention;

[0027]FIG. 9 is an explanatory view indicating differences in delay timebetween audio data and video data handled by the system of FIG. 8;

[0028]FIG. 10 is a schematic view sketching a typical setup of theinventive system;

[0029]FIG. 11 is a block diagram showing a typical structure of achannel selection device included in the setup of FIG. 10; and

[0030]FIG. 12 is a block diagram depicting a typical structure of adisplay device included in the setup of FIG. 10.

BEST MODE FOR CARRYING OUT THE INVENTION

[0031]FIG. 4 shows a typical configuration of an audio/video datatransmission and reception system practiced as a first embodiment ofthis invention. This system is basically the same in configuration asthe conventional system indicated in FIG. 1. The major difference isthat the system of FIG. 4 is supplemented with a reception buffermonitoring circuit 21 and that the reception clock generation circuit 8controls the frequency of the generated clock based on the output of thereception buffer monitoring circuit 21. The other components and theirfunctions are the same as those in the system of FIG. 1.

[0032] The basic workings of the system in FIG. 4 are the same as thoseof the system in FIG. 1 and thus will not be described further. Theinventive system differs from the system of FIG. 1 in terms of how togenerate the reception clock. This aspect of the invention is describedbelow in more detail.

[0033] The reception buffer monitoring circuit 21 monitors the size ofdata being accumulated in the reception buffer 6. When the data sizeexceeds a predetermined level, the reception clock generation circuit 8,for example, raises the frequency of the clock generated per field orper frame. When the data size becomes lower than a predetermined level,the reception clock generation circuit 8 generates the clock with alower frequency.

[0034] One way in which the reception clock generation circuit 8 variesthe frequency of the clock it generates is by using a voltage controlledoscillator (VCO). Another way to vary the clock frequency is by gettinga counter to count a clock with frequencies higher than the frequency ofthe clock fed to the audio/video decoder 7 so as to vary the countervalue for clock generation.

[0035]FIG. 5 is a flowchart of actual control steps carried out by thereception buffer monitoring circuit 21. In step S1, a check is made tosee if the size of data accumulated in the reception buffer 6 is lowerthan a predetermined low threshold. If the buffered data size is judgedto be lower than the low threshold, step S4 is reached and a check ismade to see if the clock frequency is lower than a predetermined highlimit frequency. If the clock frequency is judged lower than the highlimit frequency, then step S5 is reached in which the clock frequency islowered. If the size of data accumulated in the reception buffer 6 isjudged to be higher than the low threshold in step S1, then step S2 isreached and a check is made to see if the data size is higher than apredetermined high threshold. If the data size is judged to be higherthan the high threshold in step S2, step S6 is reached and a check ismade to see if the clock frequency is higher than a predetermined lowlimit frequency. If the clock frequency is judged higher than the lowlimit frequency in step S6, then step S7 is reached in which the clockfrequency is raised. Nothing is carried out when the size of dataaccumulated in the reception buffer 6 falls within the range between thelow threshold and the high threshold. The high and low limit frequenciesof the clock are determined in a manner meeting the followingconditions:

[0036] (1) that the frequency should not exceed a clock range in whichthe audio/video decoder operates;

[0037] (2) that the size of data in the buffer should not wildlyfluctuate; and

[0038] (3) that continued system performance should be ensured underabnormal conditions (e.g., where data fail to come in).

[0039] In step S3, a check is made to see a control stop command isissued. If the command is not judged to be issued, step S1 is reachedagain and the subsequent steps are repeated. If the control stop commandis judged to be issued in step S3, then the process is brought to anend.

[0040]FIG. 6 depicts relations between the clock input to theaudio/video encoder 1 on the one hand and the clock entered into theaudio/video decoder 7 on the other hand. It is assumed here that ftxstands for the clock input to the audio/video encoder 1 and frx for theclock entered into the audio/video decoder 7. The clock generated by thereception clock generation circuit 8 and input to the audio/videodecoder 7 is controlled within the range between a low limit clockfrequency (fl) and a high limit clock frequency (fh) by the receptionbuffer monitoring circuit 21. The audio/video decoder 7 is assumed tooperate with its frequency frx in a range between fll and fhh. It isthus required that the frequencies fl and fh fall within the aboverange, that the low limit clock frequency fl be lower than the clockftx, and that the clock ftx be lower than the high limit clock frequencyfh.

[0041]FIG. 7 graphically depicts how data sizes in the reception buffer6 vary over time. In this example, as shown in FIG. 6, when the clock isto be raised, it is brought up to the high limit clock frequency fh;when the clock is to be lowered, it is brought down to the low limitclock frequency fl. In an initial state B1 where the reception buffer 6is empty, the clock frx is brought up to the high limit clock frequencyfh so as to let data accumulate in the buffer 6. Later at a point B2where the size of data in the reception buffer 6 exceeds the highthreshold, the clock frx is judged to be in need of a reduction. Theclock frx is then brought down to the low limit clock frequency fl. At asubsequent point B3 where the data size becomes lower than the lowthreshold, the clock frx is judged to be in need of an increase. Theclock frx is then brought up again to the high limit clock frequency fh.These steps are repeated as described.

[0042]FIG. 8 shows a typical configuration of another audio/video datatransmission and reception system practiced as a second embodiment ofthis invention. With this embodiment, the audio/video encoder 1 on thetransmitting side is constituted by an audio encoder 1A and a videoencoder 1V. Correspondingly, the transmission clock generation circuit 2is made up of a transmission clock generation circuit 2A and atransmission clock generation circuit 2V. The output of the audioencoder 1A is fed to a packet assembly circuit 32 via a transmissionbuffer 31A. The output of the video encoder 1V is sent to the packetassembly circuit 32 through a transmission buffer 31V.

[0043] On the receiving side, a packet disassembly circuit 41 isfurnished corresponding to the packet assembly circuit 32 installed onthe transmitting side. The packet disassembly circuit 41 disassemblesdata received from the reception buffer 6 into an audio packet and avideo packet. The audio packet is output to an audio decoder 7A via areception buffer 42A and the video packet is sent to a video decoder 7Vthrough a reception buffer 42V.

[0044] The reception buffer 21 includes reception buffer monitoringcircuits 21A and 21V. The reception buffer monitoring circuit 21Amonitors the output from the reception buffer 42A, while the receptionbuffer monitoring circuit 21V monitors the size of data held in thereception buffer 42V. The reception clock generation circuit 8 comprisesreception clock generation circuits 8A and 8V. The reception clockgeneration circuit 8A generates a reception clock based on the output ofthe reception buffer monitoring circuit 21A and outputs the generatedclock to the audio decoder 7A. The reception clock generation circuit 8Vgenerates a reception clock based on the output of the reception buffermonitoring circuit 21V and sends the generated clock to the videodecoder 7V.

[0045] The other components and their functions are the same as those inthe system of FIG. 4.

[0046] The audio encoder 1A compresses the input transmitter data (audiodata) illustratively in MPEG format and hands the compressed data overto the transmission buffer 31A. The audio encoder 1A acts in keepingwith a transmission clock generated by the transmission clock generationcircuit 2A. The video encoder 1V operating in keeping with atransmission clock generated by the transmission clock generationcircuit 2V compresses the transmitter data (video data) illustrativelyin MPEG format and transfers the compressed data to the transmissionbuffer 31V. The package assembly circuit 32 assembles transmitterpackets by multiplexing the audio and video data from the transmissionbuffers 31A and 31V and by supplementing the result of the multiplexingwith header information or the like needed by the receiving side todisassemble the packets. The assembled transmitter packets areaccumulated in the transmission buffer 3. Every time the transmissiondevice 4 sends data, it is supplied with the next data from thetransmission buffer 3.

[0047] On the receiving side, the reception device 5 receives data andaccumulates the data in the reception buffer 6. The packet disassemblycircuit 41 disassembles the buffered data into audio data and video datawhich are transferred to the reception buffers 42A and 42V respectively.In an audio block, the reception buffer monitoring circuit 21A variesthe frequency of the clock generated by the reception clock generationcircuit 8A in keeping with the size of the data held in the receptionbuffer 42A. Based on the clock from the reception clock generationcircuit 8A, the audio decoder 7A decodes the received audio data andoutputs the decoded data as receiver data.

[0048] In a video block, the reception buffer monitoring circuit 21Vsimilarly varies the frequency of the clock generated by the receptionclock generation circuit 8V in accordance with the size of the dataretained in the reception buffer 42V. With this embodiment, audio dataand video data are separately processed by the encoders 1A and 1V and bythe decoders 7A and 7V, respectively. Because the audio and video datago through different processing paths and are subject to differences inprocessing time, the receiving side is required to synchronize the twokinds of data in delay time.

[0049]FIG. 9 schematically indicates typical differences in delay timebetween audio data and video data handled by the audio and video blocksrespectively. It is assumed here that transmitter data are input to theaudio encoder 1A and video encoder 1V in synchronism. Along theirprocessing path, the audio data are subject to a total delay time (Tda)which, except for delays in common with the video data, is made up of adelay time (Tdae) at the audio encoder 1A, a delay time (Tdat) at thetransmission buffer 31A, a delay time (Tdar) at the reception buffer42A, and a delay time (Tdad) at the audio decoder 7A. The delay time(Tdar) at the reception buffer 42A is defined as a delay time in effectat the average value (ABufAve) of the low threshold (in step S1 of FIG.5) and the high threshold (in step S2 of FIG. 5) for the audio data.

[0050] Along their processing path, the video data are subject to atotal delay time (Tdv) which, except for delays in common with the audiodata, is composed of a delay time (Tdve) at the video encoder 1V, adelay time (Tdvt) at the transmission buffer 31V, a delay time (Tdvr) atthe reception buffer 42V, and a delay time (Tdvd) at the video decoder7V. The delay time (Tdvr) at the reception buffer 42V is defined as adelay time in effect at the average value (VBufAve) of the low threshold(in step S1 of FIG. 5) and the high threshold (in step S2 of FIG. 5) forthe video data. In this example, the video data have a longer processingpath than the audio data, which translates into a longer processing timefor the video data (i.e., Tda<Tdv); the difference in processing time isTdav between the audio data and the video data.

[0051] To synchronize the audio data with the video data requiresdelaying the processing of the audio data by the time period Tdav. Thatdelay is brought about by setting suitable thresholds on the size of thedata accumulated in the reception buffer 42A. More specifically, if thesize of audio data processed in the time period Tdav is represented byABufTdav, then the audio and video data may be synchronized by settingthe center value of the accumulated audio data size as the size ABufTdavplus the average value ABufAve mentioned above. The high and lowthresholds may then be set above and below that center valuerespectively.

[0052] Although the second embodiment is designed to have the differencein delay time between the audio and the video data all compensated onthe receiving side, this is not limitative of the invention.Alternatively, the buffers on the transmitting side may be arranged toabsorb some of the delay time difference. Whereas both the audio and thevideo blocks possess clock adjusting capabilities in the secondembodiment, they are not mandatory for a system where synchronismbetween audio and video data matters little. In that kind of system, theclock adjusting function need only be furnished in either the audioblock or the video block.

[0053]FIG. 10 schematically sketches a typical setup of the inventivesystem in FIG. 4. This setup is a TV reception system that includes achannel selection device 101 and a display device 102 interconnectedwirelessly, as shown in FIG. 10. The channel selection device 101fabricated according to this invention is illustratively set up indoorsin the household. The display device 102 also fabricated according tothis invention is employed by the user at his or her side.

[0054] As shown in FIG. 10, the channel selection device 101 isconnected to an antenna cable 111 cb which is led into the householdfrom the outside where the cable is connected to an outdoor receiverantenna 111 for receiving TV broadcast signals. The channel selectiondevice 101 is also connected to a telephone line L which is led into thehousehold from the outside where the line is linked to a telephonenetwork.

[0055] A TV broadcast signal selected after reception by the antenna 111is demodulated by the channel selection device 101. The demodulatedsignal is sent wirelessly through a transmitter/receiver antenna 118 tothe display device 102. In addition, signals transmitted over thetelephone line L may be received, selected and decoded by the channelselection device 101. The decoded signal is likewise sent wirelessly viathe transmitter/receiver antenna 118 to the display device 102.

[0056] The channel selection device 101 is also capable of receivingtransmitter information such as instructions and e-mails from thedisplay device 102 through the transmitter/receiver antenna 118. Basedon the received instructions, the channel selection device 101 maychange TV broadcast signals for a new program selection or send thetransmitter information over the telephone line L.

[0057] The display device 102 receives the TV broadcast signal sentwirelessly from the channel selection device 101. On receiving thesignal, the display device 102 causes pictures represented by the videosignal contained in the received signal to appear on the screen of anLCD (liquid crystal display) 125. At the same time, the soundcorresponding to the audio signal contained in the received signal isproduced by speakers, so that the user viewing the display screen canenjoy the desired TV program.

[0058] The display device 102 also receives signals representing e-mailsand Internet website pages which were received by the channel selectiondevice 101 over the telephone line L and have been wirelesslytransmitted therefrom. The display device 102 generates display signalsbased on the received signals and causes the LCD 125 to present the userwith a display of pictures corresponding to the generated displaysignals.

[0059] Furthermore, a touch panel 351 is attached to the display screenof the LCD 125 on the display device 102. With information displayed onthe LCD 125, the user may touch on the touch panel 351 as needed toenter instructions into the system. The touch panel 351 is also used bythe user in preparing and sending outgoing e-mails as well as receivingand opening incoming e-mails addressed to the user.

[0060] As described, the channel selection device 101 acts as aninterface to admit TV broadcast signals and diverse kinds of informationoffered over the telephone line L into the TV reception system of thisinvention, and to forward information from the inventive system onto acommunication network through the telephone line L. The display device102 works as a user interface to provide the user with informationadmitted into the TV reception system through the channel selectiondevice 101 as well as to accept information entered by the user.

[0061] As shown in FIG. 10, the channel selection device 101 isinstalled in such a manner that it can be coupled securely to terminalsT1 and T2 connecting to the antennal cable 111 cb and telephone line Lrespectively, wherever the terminals are located. Since the channelselection device 101 and display device 102 are interconnectedwirelessly as illustrated, the display device 102 may be installed inany area where radio signals from the channel selection device 101 canbe received. The setup thus allows the user to enjoy desired TV programsand use e-mails through an Internet connection at locations appreciablyfreed from conventional installation constraints.

[0062]FIG. 11 is a block diagram showing a more detailed structure ofthe channel selection device 101. The components of the channelselection device 101 are placed under control of a control unit 200.

[0063] The control unit 200, as shown in FIG. 11, is a microcomputerthat comprises a CPU (central processing unit) 201, a ROM (read onlymemory) 202, a RAM (random access memory) 203, and an EEPROM(electrically erasable programmable read only memory) 204, allinterconnected via a CPU bus 206.

[0064] The ROM 202 accommodates various processing programs executed bythe channel selection device 101 as well as data needed for the programexecution. The RAM 203 serves primarily as a work area in which the dataobtained from various processes are retained temporarily.

[0065] The EEPROM 204 is a nonvolatile memory that retains theinformation held therein even when power is removed. For example, theEEPROM 204 may be used to implement what is known as a last channelmemory function. This function involves keeping information about thebroadcast channel being selected just before the main power supply ofthe channel selection device 101 was switched off, and allowing thelast-selected channel to be automatically selected when power isrestored.

[0066] As depicted in FIG. 11, the channel selection device 101 of thisembodiment has a channel selection unit 112 connected to the antennacable 111 cb coming from the outdoor receiver antenna 111 for receivingTV broadcast signals. The TV broadcast signals received by the receiverantenna 111 are supplied to the channel selection unit 112.

[0067] Out of those TV broadcast signals coming from the receiverantenna 111, the channel selection unit 112 selects the TV broadcastsignal corresponding to a channel selection instruction signal sent fromthe control unit 200. The selected TV broadcast signal is fed to ademodulation unit 113. The demodulation unit 113 demodulates thesupplied TV broadcast signal and sends the demodulated signal (i.e., TVprogram signal) to an input terminal “a” of a switching circuit 114.

[0068] The switching circuit 114, switched by a switching control signalfrom the control unit 200, allows TV program signals from thedemodulation unit 113 or signals from the control unit 200 to reach aninput terminal “a” or an input terminal “b” respectively. The signalssent from the control unit 200 to the switching circuit 114 areconstituted by e-mails and Internet website pages which have reached thechannel selection device 101 over the telephone line L and which arereceived through a modem 210.

[0069] The signal output from the switching circuit 114 is supplied to acompression processing unit 115. The compression processing unit 115compresses the supplied signal using a predetermined compression formatsuch as the MPEG (Moving Picture Expert Group) or Wavelet format.

[0070] A transmission clock generation circuit 401 placed under controlof the CPU 201 generates a transmission clock and supplies the generatedclock to the compression processing unit 115. The compressing processingunit 115 performs the above-described compression process in synchronismwith the transmission clock.

[0071] The signal compressed by the compression processing unit 115 isfed to a transmitter signal generation unit 116. In turn, thetransmitter signal generation unit 116 generates a transmitter signalbased on a predetermined communication protocol. With this embodiment,the transmitter signal is generated on the basis of IEEE (Institute ofElectrical and Electronics Engineers) 802.11 or other protocols derivedtherefrom.

[0072] The transmitter signal generated by the transmitter signalgeneration unit 116 is sent to a transmission processing unit 117S ofwireless section 117. The transmission processing unit 117S modulatesand amplifies the transmitter signal in keeping with control signalsfrom the control unit 200. The transmitter signal processed by thetransmission processing unit 117S is transmitted wirelessly through asharing unit 117K and from the transmitter/receiver antenna 118.

[0073] The sharing unit 117K is provided to prevent interference betweentransmitter and receiver signals. As described earlier, the channelselection device 101 of this embodiment is structured to receive throughthe transmitter/receiver antenna 118 instruction information sentwirelessly from the display device 102. The sharing unit 117K acts tokeep the transmitter signal from the transmission processing unit 117Sfrom interfering with the receiver signal received through the sameantenna 118.

[0074] Signals such as channel selection instructions received from thedisplay device 102 via the transmitter/receiver antenna 118 areforwarded to a reception processing unit 117R via the sharing unit 117K.The reception processing unit 117R subjects the supplied signals to suchprocesses as demodulation to turn the signals into a format that can behandled by the control unit 200. The signals thus processed are sent tothe control unit 200.

[0075] If the signal received from the reception control unit 117R isinstruction information such as channel selection instructions, then thecontrol unit 200 causes the relevant components to act accordingly. Morespecifically, if the signal sent from the reception processing unit 117Rto the control unit 200 turns out to be a channel selection instruction,then the control unit 200 supplies the channel selection unit 112 with acorresponding channel selection signal to select the designated TVbroadcast signal.

[0076] If the signal sent from the reception processing unit 117R to thecontrol unit 200 turns out to be transmitter information such as ane-mail, then the control unit 200 establishes connection with thetelephone network through the modem 210 and telephone line L, as will bedescribed later, and outputs the transmitter information over theconnected telephone network to a designated destination.

[0077] As shown in FIG. 11, the modem 210 includes an interface (I/F)unit 211 and a communication unit 212. The interface unit 211 interfacesthe channel selection device 101 with a communication line connected tothe destination through the telephone network. The interface unit 211receives signals coming over the telephone line L and transmits signalsfrom the channel selection unit 101 over the same line L.

[0078] The communication unit 212 decodes the signal received throughthe interface unit 211 and supplies the decoded signal to the controlunit 200. The communication unit 212 further encodes the transmittersignal from the control unit 200 and supplies the encoded signal to theinterface unit 211. In this manner, various kinds of data are exchangedwith the destination to which the telephone line L is connected.

[0079] As mentioned above, the channel selection device 101 of thisembodiment is capable of connecting to the Internet through the modem210, telephone line L, and a suitable ISP (Internet Service Provider).The channel selection device 101, once connected to the Internet, canobtain various kinds of information as well as send and receive e-mailsthrough the Internet connection.

[0080] The control unit 200 is capable of causing the modem 210 to gooff-hook and on-hook. Furnished with a so-called dialer function, thecontrol unit 200 may cause the modem 210 to go off-hook and send a dialsignal over the telephone line L.

[0081] As illustrated in FIG. 11, the control unit 200 is connected to akey input unit 215 having a power on/off key and diverse setting keys.Equipped with these keys, the key input unit 215 allows the user toswitch on and off the main power supply of the channel selection device101 as well as to make various settings as needed.

[0082] As described above, the channel selection device 101 of thisembodiment receives, selects, and demodulates TV broadcast signals. Thedemodulated TV broadcast signals are subjected to data compressionbefore being sent out wirelessly in accordance with a predeterminedcommunication protocol. Information supplied over the telephone line Lis also received and decoded by the channel selection device 101. Aswith the TV broadcast signals, the decoded information is subjected todata compression before being sent out wirelessly in keeping with thecommunication protocol.

[0083] The channel selection unit 101 receives instruction informationsuch as channel selection instructions transmitted wirelessly from thedisplay device 102, to be described later in more detail. Given theinstructions, the channel selection unit 101 performs correspondingprocesses. Transmitter information such as an e-mail sent from thedisplay device 102 is transmitted to its destination by the channelselection unit 101 through the modem 210.

[0084] The display device 102 to be connected wirelessly with thechannel selection device 101 will now be described. FIG. 12 is a blockdiagram depicting a typical structure of the display device 102. Thedisplay device 102 is controlled by a control unit 300 which is amicrocomputer having a CPU 301, a ROM 302, a RAM 303, and an EEPROM 304interconnected by a CPU bus 305.

[0085] The ROM 302 retains various processing programs executed by thedisplay device 102 as well as data needed for the program execution. TheRAM 303 serves primarily as a work area in which the data acquired fromvarious processes are held temporarily.

[0086] The EEPROM 304 is a nonvolatile memory that retains theinformation held therein even when power is removed. For example,various setting parameters, drafted e-mails and received e-mails may bestored in nonvolatile fashion in the EEPROM 304.

[0087] What follows is a description of how the display device 102 workswhen receiving wireless signals from the channel selection device 101. Awireless signal based on the predetermined communication protocol isreceived from the channel selection device 101 by way of atransmitter/receiver antenna 121. The received signal passes through asharing unit 122K to enter a reception processing unit 122R. Thereception processing unit 122R subjects the supplied signal to suchprocesses as demodulation, before forwarding the processed signal to adecompression processing unit 123 via a reception buffer 501.

[0088] A reception buffer monitoring circuit 502 monitors the size ofdata in the reception buffer 501 and controls a reception clockgeneration circuit 503 in accordance with the buffered data size. Undercontrol of the reception buffer monitoring circuit 502, the receptionclock generation circuit 503 generates a reception clock with afrequency corresponding to the size of data being held in the receptionbuffer 501. The generated clock is supplied to the decompressionprocessing unit 123. The decompression processing unit 123 carries outdata decompression in synchronism with the received clock.

[0089] Because the channel selection device 101 compresses all signalsbefore sending them out as described above, the decompression processingunit 123 of the display device 102 restores the original signal bydecompressing the demodulated signal coming from the channel selectiondevice 101. If the restored signal is a TV program signal, then thesignal is composed of a video signal and an audio signal which are to beseparated. The video signal is fed to a video signal processing unit 124and the audio signal to an audio signal processing unit 126.

[0090] The video signal processing unit 124 creates a display signal outof the video signal coming from the decompression processing unit 123,and sends the created display signal to an LCD 125. The LCD 125 displayspictures reflecting the video signal sent wirelessly from the channelselection device 101. Meanwhile, the audio signal processing unit 126turns the supplied signal into an audio signal to be fed to a speaker127. Given the signal, the speaker 127 produces a sound corresponding tothe audio signal transmitted wirelessly from the channel selection unit101.

[0091] As described, the display device 102 receives TV broadcastprograms and other signals sent wirelessly from the channel selectiondevice 101. The video and audio signals contained in the received signalare reproduced and output by the display device 102 so that the user mayenjoy or otherwise utilize what is being presented.

[0092] The series of steps and processes described above may be executedeither by hardware or by software.

[0093] In this specification, the steps constituting the program to bestored on a recording medium and retrieved therefrom for executionrepresent not only the processes that are carried out in the depictedsequence (i.e., on a time series basis) but also processes that areconducted parallelly or individually.

[0094] In this specification, the term “system” refers to an entireconfiguration made up of a plurality of component devices.

Industrial Applicability

[0095] This invention allows the transmitting and the receiving sides tosynchronize the data being exchanged therebetween without recourse tohaving audio/video data packets equipped with time information. Theinvention also enables audio and video data to be synchronized asneeded. This makes it possible to build an audio/video data transmissionand reception system that operates in a stable manner without the use ofMPEG transport stream packets or the like. In the inventive system,circuits for adding time-stamp information are not required on thetransmitting side while the need for clock regeneration circuits iseliminated on the receiving side. Consequently, the scale of thecomponent circuits involved is reduced significantly so that a low-costsystem can implemented.

1. A data processing apparatus comprising: receiving means for receivingdata; storing means for storing data received by said receiving means;processing means for processing the data received by said receivingmeans; clock generating means for generating a clock for use by saidprocessing means processing the data received by said receiving means;and controlling means for controlling a frequency of said clockgenerated by said clock generating means in accordance with a size ofdata stored by said storing means.
 2. A data processing apparatusaccording to claim 1, wherein said processing means decodes the datareceived by said receiving means.
 3. A data processing apparatusaccording to claim 1, wherein, if said size of data is higher than afirst reference value, then said controlling means raises the clockfrequency; and if said size of data is lower than a second referencevalue, then said controlling means lowers said clock frequency.
 4. Adata processing apparatus according to claim 3, further comprisingseparating means for separating the data received by said receivingmeans into a first data item and a second data item; wherein saidstoring means includes: first storing means for storing said first dataitem; and second storing means for storing said second data item; andwherein said processing means includes: first processing means forprocessing said first data item; and second processing means forprocessing said second data item.
 5. A data processing apparatusaccording to claim 4, wherein, if there occurs a difference in totalprocessing time between a transmission block and a reception blockhandling said first data item and said second data item, and if Buf1 isassumed to denote a data size processible by said first processing meansand Bfu2 to represent an average value of said first reference value andsaid second reference value, then said controlling means causes a centervalue of a controllable range of data sizes accommodated by said firststoring means to correspond to a sum of Buf1 and Buf2.
 6. A dataprocessing apparatus according to claim 5, wherein said first data itemand said second data item are made up of an audio data item and a videodata item respectively.
 7. A data processing method comprising the stepsof: receiving data; storing data received in said receiving step;processing the data received in said receiving step; generating a clockfor use in said processing step processing the data received in saidreceiving step; and controlling a frequency of said clock generated insaid clock generating step in accordance with a size of data stored insaid storing step.
 8. A recording medium which stores a program readableby a computer, said program comprising the steps of: receiving data;storing data received in said receiving step; processing the datareceived in said receiving step; generating a clock for use in saidprocessing step processing the data received in said receiving step; andcontrolling a frequency of said clock generated in said clock generatingstep in accordance with a size of data stored in said storing step.